The invention relates generally to integrated circuits, and more particularly to the formation of interlayer decoupling capacitors.
Advances in semiconductor manufacturing technology have led to the integration of tens, and more recently hundreds, of millions of circuit elements, such as transistors, on a single integrated circuit (IC). To achieve such dramatic increases in the density of circuit components has required semiconductor manufacturers to scale down the size of the circuit elements and the interconnection structures used to connect the circuit elements into functional circuitry, as well as scaling down the spacing between the interconnect.
When transistors in these high density integrated circuits demand high current at high frequencies, there can be both global and localized voltage drops on the power grid of the IC. This voltage drop can be reduced by providing localized sources of current, such as capacitors, which de-couple current surges from the power grid, and thereby reduce noise on the power grid. Conventionally, de-coupling capacitance in electronic systems that include ICs on printed circuit boards has been accomplished in two main ways. Firstly, through the use of off-chip capacitors which are located nearby on the printed circuit board, or incorporated into the package of the integrated circuit, and secondly, with the on-chip capacitors formed from the very thin gate dielectric layers found in MOS integrated circuits. The off-chip capacitor configuration includes parasitic inductance arising from the length of the wiring needed to connect the off-chip capacitors with the IC, which in turn limits its effectiveness for high frequency noise. The off-chip capacitors also provide little or no benefits for localized voltage droops. Additionally, extra manufacturing cost is associated with products using this approach because a separate discrete component is used. With respect to the capacitors formed with gate dielectric layers, these provide limited capacitive de-coupling due to the small area fraction of the chip that can be cost-effectively dedicated to decoupling capacitors. The limited area constrains the magnitude of the capacitance that can be achieved. In addition these gate dielectric capacitors have leakage currents which contribute to unacceptable power consumption.
What is needed are area-efficient decoupling capacitors having reduced parasitic inductances, and methods of the making these.